The present invention relates to the fabrication of semi-conductor integrated circuits. More specifically, the invention concerns the formation of marks used to align a mask or measurement overlay with a semi-conductor wafer in a photolithographic exposure apparatus, e.g., stepper or scanner.
The term "wafer" as used herein is intended to refer generally to a semiconductor substrate from which a plurality of individual chips are formed, including substrates having circuit patterns, devices and/or alignment marks formed thereon. The term is also intended to generally encompass in-process and finished semiconductor chips.
In known VLSI photolithographic processes for the production of semiconductor integrated circuits, a mask comprising a desired circuit pattern must be precisely aligned with a semiconductor wafer, or with a pattern formed on the wafer, in order to ensure proper placement of the projected image. In order to increase integration density, VLSI chips typically employ multiple layers formed by successive image projection steps. In the photo-fabrication of such multi-layer semi-conductor devices, the precise registry of the successive images is extremely critical.
Measurement overlays are used to confirm that successively projected circuit patterns have been positioned accurately with respect to each other. Obviously, the accuracy of overlay measurements depends on the accurate and precise alignment of the measurement overlays with the wafer and the circuit patterns to be checked. While the following discussion focuses principally on the problems encountered in the formation and detection of photolithographic mask alignment marks, it will be understood that similar problems exist with respect to overlay measurement marks as well, and that the present invention is applicable to both.
To obtain the necessary mask to wafer alignment, marks are placed in peripheral (kerf) regions of the mask and the wafer, respectively. These marks are detected by a photo-optical detector of the exposure tool to ascertain the precise relative positions of the mask and wafer. Then, a precision stage metrology system is used to bring the wafer and mask into proper registry.
Mask alignment marks are provided in a variety of shapes, patterns and configurations, depending upon the particular type of photo-optical detection system being utilized. Exemplary mask-wafer alignment marks and systems are described and shown in the following U.S. patents: Ayata et al. U.S. Pat. No. 4,794,648; Tanimoto et al. U.S. Pat. No. 4,769,523; Matsuura et al. U.S. Pat. No. 4,723,221; Matsuura et al. No. 4,702,606; Murakami et al. U.S. Pat. No. 4,655,598; Matsuura et al. U.S. Pat. No. 4,566,795; Imahashi U.S. Pat. No. 4,441,250; Nakazawa et al. U.S. Pat. No. 4,423,959; Imahashi U.S. Pat. No. 4,377,028; Suwa U.S. Pat. No. 4,390,279; and Suzuki et al. U.S. Pat. No. 4,315,201.
Mask alignment marks can be formed on a wafer by an additive method wherein a layer of material, e.g., chrome, is deposited on the substrate, or by a subtractive method wherein the marks are formed by etching the substrate directly. To reduce process steps and thereby attain greater production efficiency, it is desirable to combine the step of forming the alignment marks with the steps used to form the desired circuit pattern. Thus, for example, in a process for forming deep trenches to be used as capacitive elements or for device isolation, the deep trenches may be formed by selective reactive ion etching (RIE). In this step, it is possible to also etch the alignment marks to be used for alignment of a subsequently applied mask or measurement overlay. This can be accomplished by simply including in the mask and resist patterns used to form the circuit elements an additional pattern for creating alignment marks, e.g., in the kerf region(s) of the wafer.
To ensure proper detection and position determination by the photo-optical detector of the scanner or stepper, it is generally necessary to provide alignment marks on the chip which are substantially larger than the design rule of a VLSI circuit design. For example, in accordance with the 256M DRAM design rule, a deep trench has a generally rectangular shape measuring 0.55-0.8 .mu.m by 0.3 .mu.m, providing an etchable area of between 0.165 and 0.24 .mu.m.sup.2. A DRAM circuit pattern 1 comprising an array of deep trenches is illustrated in FIG. 1. Typically, the deep trenches are spaced from one another by about 0.25 .mu.m. On the other hand, conventional alignment marks formed at the deep trench (DT) level typically comprise, as shown in FIG. 2, elongated line-shaped holes 3 having a width of between 0.5 and 1.4 .mu.m and a length of 70 cm, providing a much larger etchable area of 35 to 98 .mu.m.sup.2. The alignment marks of each alignment mark pair are generally spaced from one another by about 10 .mu.m.
When a single reactive ion etching step is used to form the alignment marks and deep trenches simultaneously, a problem has been found to arise with proper detection of the marks. The problem, the inventors found, is particularly acute in the case of formation of deep trench capacitive elements of a DRAM chip, wherein the deep trenches are filled with polysilicon and then back-etched. Typically, the polysilicon filling of the trenches is accomplished by a blanket deposition of polysilicon on a patterned resist layer, such as by chemical vapor deposition (CVD). This step is followed by a chemical mechanical polishing (CMP) operation to planarize the surface and remove excess polysilicon from areas outside of the deep trenches. In this process, the elongated holes used to form the alignment marks are also filled with polysilicon and that polysilicon remains after the CMP operation. A subsequent RIE process is used to etch back the polysilicon within the deep trenches to a point slightly (e.g., 50 nm) below the surface of the silicon substrate. This etch-back step is simultaneously performed with respect to the alignment marks as well. However, within the alignment mark areas, the polysilicon etch-back depth may be insufficient to allow for proper detection of the marks by the detection apparatus.
For example, as shown in FIG. 3, the polysilicon etch back within deep trench 5 extends through an SiN film 7 and a desired distance "a" (e.g., 50 nm) below the surface of the silicon substrate. On the other hand, the resultant etch-back of the polysilicon within the alignment mark area 9 is significantly shallower, leaving the polysilicon level 11 within mark area 9 approximately level with the silicon substrate surface 13.
In one test involving alignment of gate conductor (GC) and deep trench (DT) levels, two out of 10 lots failed to produce a proper DT alignment signal. As seen in FIG. 3, one factor found to contribute to the insufficient etch depth of the marks was a difference (A-B) in the thickness of the SiN layer between the mark area and circuit pattern (cell) area following CMP polishing. This does not fully account for the problem of insufficient etch depth, however.
Under the above-described circumstances, the alignment marks are not reliably detectible using conventional edge or step height triggered photo-optical detecting apparatus. As a result, precise alignment of a mask and/or measurement overlay cannot be assured.